/* 
 * Copyright (c) 2019 Xilinx, Inc. 
 * All rights reserved.
 *
 * Author: Chris Lavin, Xilinx Research Labs.
 *  
 * This file is part of RapidWright. 
 * 
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 * 
 *     http://www.apache.org/licenses/LICENSE-2.0
 * 
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 * 
 */
/**
 * 
 */
package com.xilinx.rapidwright.device;


/**
 * Generated on: Fri Dec 06 10:46:56 2019
 * by: com.xilinx.rapidwright.release.SiteAndTileTypeUpdater
 * 
 * Enumeration of Tile type for all valid devices within Vivado.
 */
public enum TileTypeEnum {
	AMS,
	AMS_ADC_TOP,
	AMS_AMS_FILL_FT,
	AMS_AMS_FILL_TERM_T_FT,
	AMS_BRAM,
	AMS_CLB_INTF_IOB,
	AMS_CLK,
	AMS_CMT,
	AMS_DAC_TOP,
	AMS_DRP_ADC_TOP,
	AMS_DRP_DAC_TOP,
	AMS_DSP,
	AMS_INT,
	AMS_INT_L,
	AMS_INT_R,
	AMS_IOI,
	AMS_M12BUF_AMS_ALTO_AUX_IO_BOT_L_FT,
	AMS_M12BUF_AMS_ALTO_AUX_IO_TOP_L_FT,
	AMS_M12BUF_AMS_BOT_L_FT,
	AMS_M12BUF_AMS_BOT_R_FT,
	AMS_M12BUF_AMS_TOP_L_FT,
	AMS_M12BUF_AMS_TOP_R_FT,
	AMS_M12BUF_BOT_L,
	AMS_M12BUF_BOT_L_FT,
	AMS_M12BUF_BOT_R,
	AMS_M12BUF_BOT_R_FT,
	AMS_M12BUF_CTR_LEFT_AMS_ALTO_BOT_L_FT,
	AMS_M12BUF_CTR_LEFT_AMS_ALTO_TOP_L_FT,
	AMS_M12BUF_CTR_RIGHT_AMS_ALTO_BOT_L_FT,
	AMS_M12BUF_CTR_RIGHT_AMS_ALTO_TOP_L_FT,
	AMS_M12BUF_CTR_RIGHT_BOT_L_FT,
	AMS_M12BUF_CTR_RIGHT_TOP_L_FT,
	AMS_M12BUF_IO_AMS_ALTO_BOT_L_FT,
	AMS_M12BUF_IO_AMS_ALTO_TOP_L_FT,
	AMS_M12BUF_IO_AMS_BOT_L_FT,
	AMS_M12BUF_IO_AMS_TOP_L_FT,
	AMS_M12BUF_IO_BOT_L_FT,
	AMS_M12BUF_IO_BOT_R,
	AMS_M12BUF_IO_TOP_L_FT,
	AMS_M12BUF_IO_TOP_R,
	AMS_M12BUF_SYSMON_BOT_L_FT,
	AMS_M12BUF_SYSMON_TOP_L_FT,
	AMS_M12BUF_TOP_L,
	AMS_M12BUF_TOP_L_FT,
	AMS_M12BUF_TOP_R,
	AMS_M12BUF_TOP_R_FT,
	AMS_TERM_T,
	AMS_VBRK_INTF,
	BLI_BLI_FT,
	BLI_BLI_TERM_H_FT,
	BRAM,
	BRAM_BRAM_TERM_H_FT,
	BRAM_INT_INTERFACE_L,
	BRAM_INT_INTERFACE_R,
	BRAM_L,
	BRAM_R,
	BRAM_RBRK,
	BRAM_TERM_B,
	BRAM_TERM_P,
	BRAM_TERM_T,
	BRKH_BRAM,
	BRKH_B_TERM_INT,
	BRKH_CLB,
	BRKH_CLK,
	BRKH_CMT,
	BRKH_DSP_L,
	BRKH_DSP_R,
	BRKH_GTX,
	BRKH_INT,
	BRKH_INT_PSS,
	BRKH_TERM_INT,
	B_TERM_INT,
	B_TERM_INT_NOUTURN,
	B_TERM_INT_PSS,
	B_TERM_INT_SLV,
	B_TERM_VBRK,
	CFGIO_CFG_FILL_RBRK_FT,
	CFGIO_CFG_RBRK,
	CFGIO_CONFIG_RBRK,
	CFGIO_FILL_FT,
	CFGIO_IOB,
	CFGIO_IOB20,
	CFG_CENTER_BOT,
	CFG_CENTER_MID,
	CFG_CENTER_MID_SLAVE,
	CFG_CENTER_TOP,
	CFG_CENTER_TOP_SLAVE,
	CFG_CFG,
	CFG_CFG_CMAC_FILL_RBRK_FT,
	CFG_CFG_FILL_FT,
	CFG_CFG_FILL_OLY_DK_FT,
	CFG_CFG_FILL_OLY_FT,
	CFG_CFG_FILL_RBRK_FT,
	CFG_CFG_PCIE_RBRK,
	CFG_CONFIG,
	CFG_CONFIG_CMAC_RBRK_FT,
	CFG_CONFIG_HDIO_RBRK,
	CFG_CONFIG_PCIE4,
	CFG_CTR_TERM_B,
	CFG_CTR_TERM_T,
	CFG_GAP_CFGBOT,
	CFG_GAP_CFGTOP,
	CFG_M12BUF,
	CFG_M12BUF_CFG_ALTO_BOT_L_FT,
	CFG_M12BUF_CFG_ALTO_OLY_DK_BOT_L_FT,
	CFG_M12BUF_CFG_ALTO_OLY_DK_TOP_L_FT,
	CFG_M12BUF_CFG_ALTO_TERM_OLY_DK_BOT_L_FT,
	CFG_M12BUF_CFG_ALTO_TERM_OLY_DK_TOP_L_FT,
	CFG_M12BUF_CFG_ALTO_TOP_L_FT,
	CFG_M12BUF_CFG_BOT_L_FT,
	CFG_M12BUF_CFG_BOT_R,
	CFG_M12BUF_CFG_BOT_R_FT,
	CFG_M12BUF_CFG_TERM_BOT_L,
	CFG_M12BUF_CFG_TERM_TOP_L,
	CFG_M12BUF_CFG_TOP_L_FT,
	CFG_M12BUF_CFG_TOP_R,
	CFG_M12BUF_CFG_TOP_R_FT,
	CFG_M12BUF_CTR_LEFT_CFG_ALTO_TERM_BOT_L_FT,
	CFG_M12BUF_CTR_LEFT_CFG_ALTO_TERM_TOP_L_FT,
	CFG_M12BUF_CTR_LEFT_FT,
	CFG_M12BUF_CTR_RIGHT_CFG_ALTO_BOT_L_FT,
	CFG_M12BUF_CTR_RIGHT_CFG_ALTO_TOP_L_FT,
	CFG_M12BUF_CTR_RIGHT_CFG_OLY_BOT_L_FT,
	CFG_M12BUF_CTR_RIGHT_CFG_OLY_DK_BOT_L_FT,
	CFG_M12BUF_CTR_RIGHT_CFG_OLY_DK_TOP_L_FT,
	CFG_M12BUF_CTR_RIGHT_CFG_OLY_TOP_L_FT,
	CFG_M12BUF_CTR_RIGHT_FT,
	CFG_M12BUF_IO_CFG_ALTO_BOT_L_FT,
	CFG_M12BUF_IO_CFG_ALTO_OLY_DK_BOT_L_FT,
	CFG_M12BUF_IO_CFG_ALTO_OLY_DK_TOP_L_FT,
	CFG_M12BUF_IO_CFG_ALTO_TOP_L_FT,
	CFG_M12BUF_IO_CFG_BOT_L_FT,
	CFG_M12BUF_IO_CFG_BOT_R,
	CFG_M12BUF_IO_CFG_TOP_L_FT,
	CFG_M12BUF_IO_CFG_TOP_R,
	CFG_M12BUF_IO_L_FT,
	CFG_M12BUF_RBRK_L,
	CFG_M12BUF_RBRK_R,
	CFG_M12BUF_TERM_B_L,
	CFG_M12BUF_TERM_B_R,
	CFG_M12BUF_TERM_H_L_FT,
	CFG_M12BUF_TERM_H_R_FT,
	CFG_M12BUF_TERM_L,
	CFG_M12BUF_TERM_P,
	CFG_M12BUF_TERM_T_L,
	CFG_M12BUF_TERM_T_R,
	CFG_PCIE_AMS_RBRK,
	CFG_PCIE_RBRK,
	CFG_SECURITY_BOT_PELE1,
	CFG_SECURITY_MID_PELE1,
	CFG_SECURITY_TOP_PELE1,
	CFRM_AMS_CFGIO,
	CFRM_B,
	CFRM_B_RBRK,
	CFRM_CBRK_CTR_LEFT_L_FT,
	CFRM_CBRK_CTR_RIGHT_L_FT,
	CFRM_CBRK_IO_L,
	CFRM_CBRK_IO_R,
	CFRM_CBRK_L,
	CFRM_CBRK_L_RBRK,
	CFRM_CBRK_L_TERM_B,
	CFRM_CBRK_L_TERM_H_FT,
	CFRM_CBRK_L_TERM_P,
	CFRM_CBRK_L_TERM_T,
	CFRM_CBRK_R,
	CFRM_CBRK_R_RBRK,
	CFRM_CBRK_R_TERM_B,
	CFRM_CBRK_R_TERM_H_FT,
	CFRM_CBRK_R_TERM_T,
	CFRM_CFG,
	CFRM_CFRAME_DMAH_TERM_T_FT,
	CFRM_CFRAME_TERM_H_FT,
	CFRM_CONFIG,
	CFRM_L_RBRK,
	CFRM_L_TERM_B,
	CFRM_L_TERM_T,
	CFRM_RBRK_B,
	CFRM_RBRK_CFGIO,
	CFRM_RBRK_PCIE,
	CFRM_R_RBRK,
	CFRM_R_TERM_B,
	CFRM_R_TERM_T,
	CFRM_T,
	CFRM_TERM_B,
	CFRM_TERM_T,
	CFRM_T_RBRK,
	CLBLL_L,
	CLBLL_R,
	CLBLM_L,
	CLBLM_R,
	CLEL_L,
	CLEL_L_RBRK,
	CLEL_L_TERM_B,
	CLEL_L_TERM_T,
	CLEL_R,
	CLEL_R_RBRK,
	CLEL_R_TERM_B,
	CLEL_R_TERM_T,
	CLEM,
	CLEM_R,
	CLEM_RBRK,
	CLEM_TERM_B,
	CLEM_TERM_T,
	CLE_CLE_L_LEFT_TERM_H_FT,
	CLE_CLE_L_LEFT_TERM_P_FT,
	CLE_CLE_L_RIGHT_TERM_H_FT,
	CLE_CLE_M_DECAP_FT,
	CLE_CLE_M_DECAP_RBRK_FT,
	CLE_CLE_M_DECAP_TERM_H_FT,
	CLE_CLE_M_TERM_H_FT,
	CLE_L_RIGHT_TERM_P,
	CLE_L_R_RBRK,
	CLE_M,
	CLE_M_INTF_TERM_PSS_RBRK,
	CLE_M_R,
	CLE_M_RBRK,
	CLE_M_TERM_B,
	CLE_M_TERM_P,
	CLE_M_TERM_T,
	CLK_BALI_REBUF,
	CLK_BALI_REBUF_GTZ_BOT,
	CLK_BALI_REBUF_GTZ_TOP,
	CLK_BUFG_BOT_R,
	CLK_BUFG_REBUF,
	CLK_BUFG_TOP_R,
	CLK_FEED,
	CLK_HROW_BOT_R,
	CLK_HROW_TOP_R,
	CLK_IBRK_FSR2IO,
	CLK_MTBF2,
	CLK_PMV,
	CLK_PMV2,
	CLK_PMV2_SVT,
	CLK_PMVIOB,
	CLK_TERM,
	CMAC,
	CMAC_AMS_FILL_RBRK_FT,
	CMAC_AMS_RBRK_FT,
	CMAC_CMAC_AMS_RBRK_FT,
	CMAC_CMAC_CFG_TERM_T_FT,
	CMAC_CMAC_FT,
	CMAC_CMAC_LEFT_RBRK_FT,
	CMAC_CMAC_LEFT_TERM_T_FT,
	CMAC_CMAC_PCIE3_RBRK_FT,
	CMAC_CMAC_TERM_P_FT,
	CMAC_CMAC_TERM_T_FT,
	CMAC_ILKN_RBRK_FT,
	CMAC_PCIE3_CMAC_RBRK_FT,
	CMAC_PCIE4_RBRK_FT,
	CMAC_RBRK,
	CMAC_TERM_B,
	CMR_RIGHT_TERM_T,
	CMT_CMT_LEFT_TERM_P_FT,
	CMT_FIFO_L,
	CMT_FIFO_R,
	CMT_L,
	CMT_LEFT_H,
	CMT_L_RBRK,
	CMT_L_TERM_B,
	CMT_L_TERM_T,
	CMT_PMV,
	CMT_PMV_L,
	CMT_RIGHT,
	CMT_RIGHT_RBRK,
	CMT_RIGHT_TERM_B,
	CMT_TOP_L_LOWER_B,
	CMT_TOP_L_LOWER_T,
	CMT_TOP_L_UPPER_B,
	CMT_TOP_L_UPPER_T,
	CMT_TOP_R_LOWER_B,
	CMT_TOP_R_LOWER_T,
	CMT_TOP_R_UPPER_B,
	CMT_TOP_R_UPPER_T,
	DSP,
	DSP_JTAG_TERM_P,
	DSP_L,
	DSP_R,
	DSP_RBRK,
	DSP_TERM_B,
	DSP_TERM_P,
	DSP_TERM_T,
	FE_FE_FT,
	FE_FE_RBRK_FT,
	FE_FE_TERM_B_FT,
	FE_FE_TERM_T_FT,
	FSR_GAP,
	FSR_GAP50_MINICBRK_FT,
	FSR_GAP50_MINICBRK_RBRK_FT,
	FSR_GAP50_MINICBRK_TERM_B_FT,
	FSR_GAP50_MINICBRK_TERM_T_FT,
	FSR_GAP_RBRK,
	FSR_GAP_TERM_B,
	FSR_GAP_TERM_T,
	GTH_CHANNEL_0,
	GTH_CHANNEL_1,
	GTH_CHANNEL_2,
	GTH_CHANNEL_3,
	GTH_COMMON,
	GTH_DA0_TERM_L_FT,
	GTH_DA0_TERM_L_RBRK_FT,
	GTH_DA0_TERM_L_TERM_P_FT,
	GTH_DA0_TERM_L_TERM_T_FT,
	GTH_DA7_TERM_L,
	GTH_DA7_TERM_L_RBRK,
	GTH_DA7_TERM_L_TERM_P,
	GTH_DA7_TERM_L_TERM_T,
	GTH_INT_INTERFACE,
	GTH_INT_INTERFACE_L,
	GTH_QUAD_HPIO_RBRK_FT,
	GTH_QUAD_HPIO_RIGHT_RBRK,
	GTH_QUAD_LEFT,
	GTH_QUAD_LEFT_DA0_TERM_P_FT,
	GTH_QUAD_LEFT_DA7_TERM_P,
	GTH_QUAD_LEFT_FT,
	GTH_QUAD_LEFT_RBRK,
	GTH_QUAD_LEFT_RBRK_FT,
	GTH_QUAD_LEFT_TERM_T,
	GTH_QUAD_LEFT_TERM_T_FT,
	GTH_QUAD_RIGHT,
	GTH_QUAD_RIGHT_RBRK,
	GTH_QUAD_RIGHT_TERM_B_FT,
	GTH_QUAD_RIGHT_TERM_T,
	GTH_R,
	GTH_R_RBRK,
	GTH_R_TERM_B,
	GTH_R_TERM_T,
	GTM_DUAL_LEFT_FT,
	GTM_DUAL_LEFT_RBRK_FT,
	GTM_DUAL_LEFT_TERM_B_FT,
	GTM_DUAL_LEFT_TERM_T_FT,
	GTM_DUAL_RIGHT_FT,
	GTM_DUAL_RIGHT_RBRK_FT,
	GTM_DUAL_RIGHT_TERM_B_FT,
	GTM_DUAL_RIGHT_TERM_T_FT,
	GTP_CHANNEL_0,
	GTP_CHANNEL_0_MID_LEFT,
	GTP_CHANNEL_0_MID_RIGHT,
	GTP_CHANNEL_1,
	GTP_CHANNEL_1_MID_LEFT,
	GTP_CHANNEL_1_MID_RIGHT,
	GTP_CHANNEL_2,
	GTP_CHANNEL_2_MID_LEFT,
	GTP_CHANNEL_2_MID_RIGHT,
	GTP_CHANNEL_3,
	GTP_CHANNEL_3_MID_LEFT,
	GTP_CHANNEL_3_MID_RIGHT,
	GTP_COMMON,
	GTP_COMMON_MID_LEFT,
	GTP_COMMON_MID_RIGHT,
	GTP_INT_INTERFACE,
	GTP_INT_INTERFACE_L,
	GTP_INT_INTERFACE_R,
	GTP_INT_INT_TERM_L,
	GTP_INT_INT_TERM_R,
	GTP_MID_CHANNEL_STUB,
	GTP_MID_COMMON_STUB,
	GTX_CHANNEL_0,
	GTX_CHANNEL_1,
	GTX_CHANNEL_2,
	GTX_CHANNEL_3,
	GTX_COMMON,
	GTX_INT_INTERFACE,
	GTX_INT_INTERFACE_L,
	GTY_ALTO_TERM_L_FT,
	GTY_ALTO_TERM_L_RBRK_FT,
	GTY_ALTO_TERM_L_TERM_P_FT,
	GTY_ALTO_TERM_L_TERM_T_FT,
	GTY_DC0_TERM_L_FT,
	GTY_DC0_TERM_L_RBRK_FT,
	GTY_DC0_TERM_L_TERM_P_FT,
	GTY_DC0_TERM_L_TERM_T_FT,
	GTY_L,
	GTY_L_RBRK,
	GTY_L_TERM_B,
	GTY_L_TERM_T,
	GTY_QUAD_LEFT_DC0_TERM_P_FT,
	GTY_QUAD_LEFT_FT,
	GTY_QUAD_LEFT_RBRK_FT,
	GTY_QUAD_LEFT_TERM_B_FT,
	GTY_QUAD_LEFT_TERM_H_FT,
	GTY_QUAD_LEFT_TERM_P_FT,
	GTY_QUAD_LEFT_TERM_T_FT,
	GTY_QUAD_RIGHT_TERM_H_FT,
	GTY_R,
	GTY_R_RBRK,
	GTY_R_TERM_B,
	GTY_R_TERM_T,
	GTZ_BOT,
	GTZ_BRAM,
	GTZ_CLB_INTF_IOB,
	GTZ_CLK,
	GTZ_CLK_B,
	GTZ_CMT,
	GTZ_DSP,
	GTZ_INT,
	GTZ_INT_L,
	GTZ_INT_LB,
	GTZ_INT_R,
	GTZ_INT_RB,
	GTZ_IOI,
	GTZ_TOP,
	GTZ_VBRK_INTF,
	HBM_DMAH_FT,
	HCLK_BRAM,
	HCLK_CLB,
	HCLK_CMT,
	HCLK_CMT_L,
	HCLK_DSP_L,
	HCLK_DSP_R,
	HCLK_FEEDTHRU_1,
	HCLK_FEEDTHRU_1_PELE,
	HCLK_FEEDTHRU_2,
	HCLK_FIFO_L,
	HCLK_GTX,
	HCLK_INT_INTERFACE,
	HCLK_IOB,
	HCLK_IOI,
	HCLK_IOI3,
	HCLK_L,
	HCLK_L_BOT_UTURN,
	HCLK_L_SLV,
	HCLK_L_TOP_UTURN,
	HCLK_R,
	HCLK_R_BOT_UTURN,
	HCLK_R_SLV,
	HCLK_R_TOP_UTURN,
	HCLK_TERM,
	HCLK_TERM_GTX,
	HCLK_VBRK,
	HCLK_VFRAME,
	HDIO_AMS_RBRK,
	HDIO_BOT_RIGHT,
	HDIO_HDIO_FILL_AMS_FILL_RBRK_FT,
	HDIO_HDIO_FILL_FT,
	HDIO_HDIO_FILL_PCIE4_RBRK_FT,
	HDIO_HDIO_FILL_RBRK_FT,
	HDIO_HDIO_FILL_TERM_T_FT,
	HDIO_HDIO_RIGHT_TERM_P_FT,
	HDIO_HDIO_RIGHT_TERM_RBRK_FT,
	HDIO_ILKN_RBRK_FT,
	HDIO_PCIE4_RBRK_FT,
	HDIO_RIGHT_CFG_TERM_T,
	HDIO_RIGHT_RBRK,
	HDIO_RIGHT_TERM_B,
	HDIO_RIGHT_TERM_T,
	HDIO_TOP_RIGHT,
	HPHRIO_RBRK_L,
	HPIO_AMS_BOT_TERM_R,
	HPIO_AMS_BOT_TERM_R_GTH,
	HPIO_AMS_TOP_TERM_R,
	HPIO_AMS_TOP_TERM_R_GTH,
	HPIO_AUX_IO_TERM_L_BOT_DA6_FT,
	HPIO_AUX_IO_TERM_L_BOT_FT,
	HPIO_AUX_IO_TERM_L_TOP_DA6_FT,
	HPIO_AUX_IO_TERM_L_TOP_FT,
	HPIO_CBRK_IO,
	HPIO_CFG_BOT_TERM_R,
	HPIO_CFG_BOT_TERM_R_GTH,
	HPIO_CFG_TERM_L_BOT_FT,
	HPIO_CFG_TERM_L_TOP_FT,
	HPIO_CFG_TOP_TERM_R,
	HPIO_CFG_TOP_TERM_R_GTH,
	HPIO_HPIO_LEFT_TERM_B_L_FT,
	HPIO_HPIO_LEFT_TERM_P_FT,
	HPIO_HPIO_LEFT_TERM_T_L_FT,
	HPIO_HPIO_TERM_B_LEFT_OUTER_FT,
	HPIO_HPIO_TERM_H_FT,
	HPIO_HPIO_TERM_T_LEFT_OUTER_FT,
	HPIO_K3_TERM_L_FT,
	HPIO_K3_TERM_L_RBRK_FT,
	HPIO_K3_TERM_L_TERM_B_FT,
	HPIO_L,
	HPIO_L_RBRK,
	HPIO_L_TERM_B,
	HPIO_L_TERM_T,
	HPIO_RBRK_L,
	HPIO_RIGHT,
	HPIO_RIGHT_RBRK,
	HPIO_RIGHT_TERM_B,
	HPIO_RIGHT_TERM_T,
	HPIO_TERM_B_L,
	HPIO_TERM_L,
	HPIO_TERM_L_DA6_FT,
	HPIO_TERM_L_DA6_RBRK_FT,
	HPIO_TERM_L_DA6_TERM_P_FT,
	HPIO_TERM_L_DA6_TERM_T_FT,
	HPIO_TERM_L_FT,
	HPIO_TERM_L_RBRK,
	HPIO_TERM_L_RBRK_FT,
	HPIO_TERM_L_TERM_B_FT,
	HPIO_TERM_L_TERM_T_FT,
	HPIO_TERM_R_GTH_RBRK,
	HPIO_TERM_R_GTH_TERM_B,
	HPIO_TERM_R_RBRK,
	HPIO_TERM_R_TERM_B,
	HPIO_TERM_R_TERM_T,
	HPIO_TERM_T_L,
	HPIO_VH_TERM_L_FT,
	HPIO_VH_TERM_L_RBRK_FT,
	HPIO_VH_TERM_L_TERM_B_FT,
	HPIO_VH_TERM_L_TERM_T_FT,
	HRIO_L,
	HRIO_RBRK_L,
	HRIO_TERM_B_L,
	HSADC_HSADC_RIGHT_FT,
	HSADC_HSADC_RIGHT_RBRK_FT,
	HSADC_HSADC_RIGHT_TERM_B_FT,
	HSADC_HSC_FILL_RIGHT_FT,
	HSDAC_HSDAC_HSADC_RIGHT_RBRK_FT,
	HSDAC_HSDAC_RIGHT_FT,
	HSDAC_HSDAC_RIGHT_RBRK_FT,
	HSDAC_HSDAC_RIGHT_TERM_T_FT,
	ILKN_AMS_FILL_RBRK_FT,
	ILKN_AMS_RBRK_FT,
	ILKN_CMAC_RBRK_FT,
	ILKN_HDIO_FILL_RBRK_FT,
	ILKN_HDIO_RBRK_FT,
	ILKN_ILKN_CFG_TERM_T_FT,
	ILKN_ILKN_FT,
	ILKN_ILKN_RBRK_FT,
	ILKN_PCIE4_RBRK_FT,
	ILMAC_CMAC_ILMAC_LEFT_RBRK_FT,
	ILMAC_ILMAC_AMS_RBRK_FT,
	ILMAC_ILMAC_CMAC_LEFT_RBRK_FT,
	ILMAC_ILMAC_CMAC_RBRK_FT,
	ILMAC_ILMAC_FT,
	ILMAC_ILMAC_LEFT_TERM_B_FT,
	ILMAC_ILMAC_PCIE3_RBRK_FT,
	ILMAC_PCIE3_ILMAC_RBRK_FT,
	INT,
	INT_FEEDTHRU_1,
	INT_FEEDTHRU_2,
	INT_IBRK_FSR2FE_FT,
	INT_IBRK_FSR2FE_RBRK_FT,
	INT_IBRK_FSR2FE_TERM_B_FT,
	INT_IBRK_FSR2FE_TERM_T_FT,
	INT_IBRK_FSR2IO,
	INT_IBRK_FSR2IO_R,
	INT_IBRK_FSR2IO_RBRK,
	INT_IBRK_FSR2IO_RBRK_R,
	INT_IBRK_FSR2IO_TERM_B,
	INT_IBRK_FSR2IO_TERM_B_L_FT,
	INT_IBRK_FSR2IO_TERM_B_R,
	INT_IBRK_FSR2IO_TERM_H_FT,
	INT_IBRK_FSR2IO_TERM_P_FT,
	INT_IBRK_FSR2IO_TERM_T,
	INT_IBRK_FSR2IO_TERM_T_L_FT,
	INT_IBRK_FSRIO_TERM_T_R,
	INT_IBRK_IO,
	INT_IBRK_IO2XIPHY,
	INT_IBRK_IO_R,
	INT_IBRK_IO_RBRK,
	INT_IBRK_IO_R_RBRK,
	INT_IBRK_IO_R_TERM_T,
	INT_IBRK_IO_TERM_B,
	INT_IBRK_IO_TERM_P_FT,
	INT_IBRK_IO_TERM_T,
	INT_IBRK_LEFT_L_FT,
	INT_IBRK_L_R,
	INT_IBRK_RBRK_FSR2IO,
	INT_IBRK_RBRK_IO2XIPHY,
	INT_IBRK_RBRK_LEFT_L_FT,
	INT_IBRK_RBRK_L_R,
	INT_IBRK_RBRK_R_L,
	INT_IBRK_RBRK_XIPHY2INT,
	INT_IBRK_R_L,
	INT_IBRK_R_TERM_B,
	INT_IBRK_TERM_B_FSR2IO,
	INT_IBRK_TERM_B_IO2XIPHY,
	INT_IBRK_TERM_B_LEFT_L_FT,
	INT_IBRK_TERM_B_L_R,
	INT_IBRK_TERM_B_OUTER_FT,
	INT_IBRK_TERM_B_R_L,
	INT_IBRK_TERM_B_XIPHY2INT,
	INT_IBRK_TERM_T_FSR2IO,
	INT_IBRK_TERM_T_IO2XIPHY,
	INT_IBRK_TERM_T_LEFT_L_FT,
	INT_IBRK_TERM_T_L_R,
	INT_IBRK_TERM_T_OUTER_FT,
	INT_IBRK_TERM_T_R_L,
	INT_IBRK_TERM_T_XIPHY2INT,
	INT_IBRK_XIPHY2INT,
	INT_INTERFACE_GT_R,
	INT_INTERFACE_GT_R_RBRK,
	INT_INTERFACE_GT_R_TERM_B,
	INT_INTERFACE_GT_R_TERM_T,
	INT_INTERFACE_L,
	INT_INTERFACE_L_RBRK,
	INT_INTERFACE_L_TERM_B,
	INT_INTERFACE_L_TERM_T,
	INT_INTERFACE_PCIE_L,
	INT_INTERFACE_PCIE_L_RBRK,
	INT_INTERFACE_PCIE_L_TERM_B,
	INT_INTERFACE_PCIE_L_TERM_T,
	INT_INTERFACE_PCIE_R,
	INT_INTERFACE_PCIE_R_RBRK,
	INT_INTERFACE_PCIE_R_TERM_B,
	INT_INTERFACE_PCIE_R_TERM_T,
	INT_INTERFACE_PSS_L,
	INT_INTERFACE_R,
	INT_INTERFACE_R_RBRK,
	INT_INTERFACE_R_TERM_B,
	INT_INTERFACE_R_TERM_T,
	INT_INTF_L,
	INT_INTF_LEFT_IBRK_IO_TERM_H_FT,
	INT_INTF_LEFT_IBRK_PCIE4_TERM_H_FT,
	INT_INTF_LEFT_IBRK_PCIE4_TERM_P_FT,
	INT_INTF_LEFT_TERM_GT_TERM_H_FT,
	INT_INTF_LEFT_TERM_GT_TERM_P,
	INT_INTF_LEFT_TERM_H_FT,
	INT_INTF_LEFT_TERM_IO_FT,
	INT_INTF_LEFT_TERM_IO_RBRK_FT,
	INT_INTF_LEFT_TERM_IO_TERM_B_FT,
	INT_INTF_LEFT_TERM_IO_TERM_P_FT,
	INT_INTF_LEFT_TERM_IO_TERM_T_FT,
	INT_INTF_LEFT_TERM_P,
	INT_INTF_LEFT_TERM_PSS,
	INT_INTF_LEFT_TERM_PSS_RBRK,
	INT_INTF_LEFT_TERM_PSS_TERM_B,
	INT_INTF_LEFT_TERM_PSS_TERM_T,
	INT_INTF_LEFT_TERM_PSS_TERM_V_FT,
	INT_INTF_L_CMT,
	INT_INTF_L_IO,
	INT_INTF_L_IO_RBRK,
	INT_INTF_L_IO_TERM_B,
	INT_INTF_L_IO_TERM_T,
	INT_INTF_L_PCIE4,
	INT_INTF_L_PCIE4_RBRK,
	INT_INTF_L_PCIE4_TERM_B,
	INT_INTF_L_PCIE4_TERM_T,
	INT_INTF_L_RBRK,
	INT_INTF_L_TERM_B,
	INT_INTF_L_TERM_GT,
	INT_INTF_L_TERM_GT_RBRK,
	INT_INTF_L_TERM_G_TERM_B,
	INT_INTF_L_TERM_G_TERM_T,
	INT_INTF_L_TERM_T,
	INT_INTF_R,
	INT_INTF_RIGHT_IBRK_PCIE4_TERM_H_FT,
	INT_INTF_RIGHT_IBRK_PCIE4_TERM_P_FT,
	INT_INTF_RIGHT_IO_RBRK,
	INT_INTF_RIGHT_IO_TERM_B,
	INT_INTF_RIGHT_TERM_GT_IO_RBRK,
	INT_INTF_RIGHT_TERM_GT_TERM_H_FT,
	INT_INTF_RIGHT_TERM_H_FT,
	INT_INTF_RIGHT_TERM_IO,
	INT_INTF_RIGHT_TERM_IO_TERM_T,
	INT_INTF_RIGHT_TERM_P,
	INT_INTF_R_PCIE4,
	INT_INTF_R_PCIE4_RBRK,
	INT_INTF_R_PCIE4_TERM_B,
	INT_INTF_R_PCIE4_TERM_T,
	INT_INTF_R_RBRK,
	INT_INTF_R_TERM_B,
	INT_INTF_R_TERM_GT,
	INT_INTF_R_TERM_GT_RBRK,
	INT_INTF_R_TERM_GT_TERM_B,
	INT_INTF_R_TERM_GT_TERM_T,
	INT_INTF_R_TERM_T,
	INT_INT_INTERFACE_GT_LEFT_FT,
	INT_INT_INTERFACE_GT_LEFT_RBRK_FT,
	INT_INT_INTERFACE_GT_LEFT_TERM_B_FT,
	INT_INT_INTERFACE_GT_LEFT_TERM_T_FT,
	INT_INT_INTERFACE_XIPHY_FT,
	INT_INT_INTERFACE_XIPHY_RBRK_FT,
	INT_INT_INTERFACE_XIPHY_TERM_B_FT,
	INT_INT_INTERFACE_XIPHY_TERM_T_FT,
	INT_INT_TERM_H_FT,
	INT_L,
	INT_L_SLV,
	INT_L_SLV_FLY,
	INT_R,
	INT_RBRK,
	INT_R_SLV,
	INT_R_SLV_FLY,
	INT_TERM_B,
	INT_TERM_IO_TERM_T,
	INT_TERM_L_IO,
	INT_TERM_L_IO_RBRK,
	INT_TERM_L_IO_TERM_B,
	INT_TERM_P,
	INT_TERM_T,
	IO_INT_INTERFACE_L,
	IO_INT_INTERFACE_R,
	LAGUNA_TERM_B,
	LAGUNA_TERM_T,
	LAGUNA_TILE,
	LAG_C2L_RBRK,
	LAG_CLEM2LAGUNA_RBRK_FT,
	LAG_LAG,
	LAG_LAG2C_RBRK,
	LAG_LAGUNA2CLEM_RBRK_FT,
	LAG_LAG_TERM_B,
	LAG_LAG_TERM_T,
	LIOB18,
	LIOB18_SING,
	LIOB33,
	LIOB33_SING,
	LIOI,
	LIOI3,
	LIOI3_SING,
	LIOI3_TBYTESRC,
	LIOI3_TBYTETERM,
	LIOI_SING,
	LIOI_TBYTESRC,
	LIOI_TBYTETERM,
	L_TERM_INT,
	L_TERM_INT_BRAM,
	MONITOR_BOT,
	MONITOR_BOT_FUJI2,
	MONITOR_BOT_PELE1,
	MONITOR_BOT_SLAVE,
	MONITOR_MID,
	MONITOR_MID_FUJI2,
	MONITOR_MID_PELE1,
	MONITOR_TOP,
	MONITOR_TOP_FUJI2,
	MONITOR_TOP_PELE1,
	NULL,
	PCIE,
	PCIE3_BOT_RIGHT,
	PCIE3_INT_INTERFACE_L,
	PCIE3_INT_INTERFACE_R,
	PCIE3_RIGHT,
	PCIE3_TOP_RIGHT,
	PCIE4C_PCIE4C_FT,
	PCIE4_AMS_FILL_RBRK_FT,
	PCIE4_AMS_RBRK_FT,
	PCIE4_CFG_TERM_T_FT,
	PCIE4_CMAC_RBRK_FT,
	PCIE4_PCIE4_FT,
	PCIE4_PCIE4_RBRK_FT,
	PCIE4_TERM_B_FT,
	PCIE4_TERM_H_FT,
	PCIE4_TERM_T_FT,
	PCIE_BOT,
	PCIE_BOT_LEFT,
	PCIE_INT_INTERFACE_L,
	PCIE_INT_INTERFACE_LEFT_L,
	PCIE_INT_INTERFACE_R,
	PCIE_NULL,
	PCIE_TOP,
	PCIE_TOP_LEFT,
	PSS0,
	PSS1,
	PSS2,
	PSS3,
	PSS4,
	PSS_ALTO,
	PSS_ALTO_TERM_B,
	PSS_ALTO_TERM_T,
	PSS_ALTO_VCU_DA6_RBRK_FT,
	PSS_DA6_FILL_ALTO_FT,
	PSS_GTH_FILL_DA0_FT,
	PSS_GTH_FILL_DA0_TERM_B_FT,
	PSS_GTH_FILL_DA7,
	PSS_GTH_FILL_DA7_TERM_B,
	PSS_GTY_FILL_ALTO_FT,
	PSS_GTY_FILL_ALTO_TERM_B_FT,
	PSS_VCU_DA6_FILL_ALTO_RBRK_FT,
	RCLK_AMS_CFGIO,
	RCLK_BRAM_INTF_L,
	RCLK_BRAM_INTF_TD_L,
	RCLK_BRAM_INTF_TD_R,
	RCLK_BRAM_L,
	RCLK_BRAM_R,
	RCLK_CBRK_IO,
	RCLK_CBRK_IO_M12BUF_R,
	RCLK_CBRK_L,
	RCLK_CBRK_M12BUF_L,
	RCLK_CBRK_M12BUF_R,
	RCLK_CBRK_R,
	RCLK_CLEL_L,
	RCLK_CLEL_L_L,
	RCLK_CLEL_L_R,
	RCLK_CLEL_R,
	RCLK_CLEL_R_L,
	RCLK_CLEL_R_R,
	RCLK_CLEM_CLKBUF_L,
	RCLK_CLEM_L,
	RCLK_CLEM_R,
	RCLK_CLE_M_L,
	RCLK_CLE_M_R,
	RCLK_DSP_CLKBUF_L,
	RCLK_DSP_INTF_CLKBUF_L,
	RCLK_DSP_INTF_L,
	RCLK_DSP_INTF_R,
	RCLK_DSP_L,
	RCLK_DSP_R,
	RCLK_GAP4,
	RCLK_HDIO,
	RCLK_HPIO_L,
	RCLK_HPIO_R,
	RCLK_HPIO_TERM_R,
	RCLK_HPIO_TERM_R_GTH,
	RCLK_HRIO_L,
	RCLK_IBRK_FSR2IO,
	RCLK_IBRK_FSR2IO_R,
	RCLK_IBRK_IO,
	RCLK_IBRK_IO2XIPHY,
	RCLK_IBRK_IO_R,
	RCLK_IBRK_L_R,
	RCLK_IBRK_R_L,
	RCLK_IBRK_XIPHY2INT,
	RCLK_INTF_GT_R_R,
	RCLK_INTF_LEFT_TERM_ALTO,
	RCLK_INTF_LEFT_TERM_DA7,
	RCLK_INTF_L_IBRK_IO_L,
	RCLK_INTF_L_IBRK_PCIE4_L,
	RCLK_INTF_L_IBRK_PCIE4_R,
	RCLK_INTF_L_L,
	RCLK_INTF_L_R,
	RCLK_INTF_L_TERM_GT,
	RCLK_INTF_PCIE_L_R,
	RCLK_INTF_PCIE_R_L,
	RCLK_INTF_RIGHT_TERM_GT_IO,
	RCLK_INTF_RIGHT_TERM_IO,
	RCLK_INTF_R_IBRK_L,
	RCLK_INTF_R_L,
	RCLK_INTF_R_R,
	RCLK_INTF_R_TERM_GT,
	RCLK_INT_L,
	RCLK_INT_R,
	RCLK_INT_TERM_L,
	RCLK_LAG_L,
	RCLK_LAG_R,
	RCLK_RCLK_BRAM_L_AUXCLMP_FT,
	RCLK_RCLK_BRAM_L_BRAMCLMP_FT,
	RCLK_RCLK_CBRK_CTR_LEFT_M12BUF_L_FT,
	RCLK_RCLK_CBRK_CTR_RIGHT_M12BUF_L_FT,
	RCLK_RCLK_CBRK_IO_M12BUF_L_FT,
	RCLK_RCLK_CLE_M_DECAP_L_FT,
	RCLK_RCLK_CLE_M_DECAP_R_FT,
	RCLK_RCLK_CTR_FILL_FT,
	RCLK_RCLK_DSP_INTF_DC12_L_FT,
	RCLK_RCLK_DSP_INTF_DC12_R_FT,
	RCLK_RCLK_GAP50_MINICBRK_FT,
	RCLK_RCLK_HPIO_TERM_L_DA6_FT,
	RCLK_RCLK_HPIO_TERM_L_FT,
	RCLK_RCLK_IBRK_FSR2FE_FT,
	RCLK_RCLK_IBRK_LEFT_L_FT,
	RCLK_RCLK_INTF_GTH_LEFT_L_FT,
	RCLK_RCLK_INTF_GT_LEFT_L_FT,
	RCLK_RCLK_INTF_LEFT_IBRK_FE_L_FT,
	RCLK_RCLK_INTF_LEFT_TERM_DA0_FT,
	RCLK_RCLK_INTF_LEFT_TERM_DA6_FT,
	RCLK_RCLK_INTF_LEFT_TERM_DA8_FT,
	RCLK_RCLK_INTF_LEFT_TERM_DC12_FT,
	RCLK_RCLK_INTF_LEFT_TERM_IO_FT,
	RCLK_RCLK_INTF_PCIE3_LEFT_L_FT,
	RCLK_RCLK_INTF_XIPHY_LEFT_L_FT,
	RCLK_RCLK_K3_TERM_L_FT,
	RCLK_RCLK_LAGUNA_L_FT,
	RCLK_RCLK_LAGUNA_R_FT,
	RCLK_RCLK_URAM_INTF_L_FT,
	RCLK_RCLK_VH_TERM_L_FT,
	RCLK_RCLK_XIPHY_INNER_FT,
	RCLK_TERM_L,
	RCLK_XIPHY_OUTER_RIGHT,
	RIOB18,
	RIOB18_SING,
	RIOB33,
	RIOB33_SING,
	RIOI,
	RIOI3,
	RIOI3_SING,
	RIOI3_TBYTESRC,
	RIOI3_TBYTETERM,
	RIOI_SING,
	RIOI_TBYTESRC,
	RIOI_TBYTETERM,
	R_TERM_INT,
	R_TERM_INT_GTX,
	TERM_CMT,
	T_TERM_INT,
	T_TERM_INT_NOUTURN,
	T_TERM_INT_SLV,
	URAM_URAM_DELAY_FT,
	URAM_URAM_FT,
	URAM_URAM_RBRK_FT,
	URAM_URAM_TERM_B_FT,
	URAM_URAM_TERM_H_FT,
	URAM_URAM_TERM_P_FT,
	URAM_URAM_TERM_T_FT,
	VBRK,
	VBRK_EXT,
	VCU_DA6_FILL_FT,
	VCU_VCU_DA4_TERM_V_FT,
	VCU_VCU_DA6_TERM_V_FT,
	VCU_VCU_FT,
	VCU_VCU_TERM_V_FT,
	VFRAME,
	XIPHY_BYTE_L,
	XIPHY_BYTE_RIGHT,
	XIPHY_L,
	XIPHY_L_RBRK,
	XIPHY_L_TERM_B,
	XIPHY_L_TERM_T,
	XIPHY_RIGHT_RBRK,
	XIPHY_RIGHT_TERM_R_FT,
	XIPHY_RIGHT_TERM_T_FT,
	XIPHY_XIPHY_LEFT_TERM_P_FT,
}
